MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 365
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Bits
4–3
1–0
7
6
5
2
RxIRQ/FF
RxRTS
Name
ERR
ULL
B/C
PM
PT
Receiver request-to-send. Allows the RTS output to control the CTS input of the transmitting device to
prevent receiver overrun. If both the receiver and transmitter are incorrectly programmed for RTS control,
RTS control is disabled for both. Transmitter RTS control is configured in UMR2n[TxRTS].
0 The receiver has no effect on RTS.
1 When a valid start bit is received, RTS is negated if the UART's FIFO is full. RTS is reasserted when the
If RTS is controlled by the fill level of the receiver FIFO via UACRn[RTSL], this bit should be cleared.
Receiver interrupt select.
0 RxRDY is the source that generates IRQ.
1 FFULL is the source that generates IRQ.
If more detail on the status of the FIFO is required, UISRn{RxFIFO] indicates a change in the FIFO status
as programmed in URFn[RXS].
Error mode. Configures the FIFO status bits, USRn[RB,FE,PE].
0 Character mode. The USRn values reflect the status of the character at the top of the FIFO. ERR must
1 Block mode. The USRn values are the logical OR of the status for all characters reaching the top of the
Parity mode. Selects the parity or multidrop mode for the channel. The parity bit is added to the transmitted
character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown
below.
Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address
character is transmitted (PM = 11).
Bits per character. Select the number of data bits per character to be sent. The values shown do not include
start, parity, or stop bits.
00 5 bits
01 6 bits
10 7 bits
11 8 bits
FIFO has an empty position available.
be 0 for correct A/D flag information when in multidrop mode.
FIFO because the last
“UART Command Registers
PM
00
01
10
11
MCF5272 ColdFire
With parity
Force parity
No parity
Multidrop mode
Parity Mode
Table 16-2. UMR1n Field Descriptions
RESET ERROR STATUS
®
Integrated Microprocessor User’s Manual, Rev. 3
(UCRn).”
Even parity
Low parity
Data character
Parity Type (PT= 0)
Description
command for the channel was issued. See
n/a
Odd parity
High parity
Address character
Parity Type (PT= 1)
Section 16.3.5,
UART Modules
16-5
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