MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 341
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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14.3.1
The module provides as many as 15 ports and a total of seven signals: QSPI_Dout, QSPI_Din, QSPI_CLK,
QSPI_CS0, QSPI_CS1, QSPI_CS2, and QSPI_CS3.
Peripheral chip-select signals, QSPI_CS[0:3], are used to select an external device as the source or
destination for serial data transfer. Signals are asserted at a logic level corresponding to the value of the
QSPI_CS[3:0] bits in the command RAM whenever a command in the queue is executed. More than one
chip-select signal can be asserted simultaneously.
Although QSPI_CS[0:3] will function as simple chip selects in most applications, up to 15 ports can be
selected by decoding them with an external 4-to-16 decoder.
Note that chip selects QSPI_CS[3:1] are multiplexed with other pin functions. QSPI_Dout, QSPI_CLK,
and QSPI_CS0 are multiplexed with MCF5272 configuration inputs that only function during system
reset.
14.3.2
Because the QSPI module only operates in master mode, the master bit in the QSPI mode register
(QMR[MSTR]) must be set for the QSPI to function properly. The QSPI can initiate serial transfers but
cannot respond to transfers initiated by other QSPI masters.
14.4
The QSPI uses a dedicated 80-byte block of static RAM accessible both to the module and the CPU to
perform queued operations. The RAM is divided into three segments as follows:
RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive
data comprise 1 queue entry, 0x0–0xF.
The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit
data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued
commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their
completion. Optionally, QIR[SPIFE] can be enabled to generate an interrupt.
Freescale Semiconductor
•
•
•
16 command control bytes (command RAM)
16 transmit data words, (transfer RAM)
16 receive data words (transfer RAM)
Operation
QSPI Data Output (QSPI_Dout)
QSPI Data Input (QSPI_Din)
Serial Clock (QSPI_CLK)
Peripheral Chip Selects (QSPI_CS[3:0])
Interface and Pins
Internal Bus Interface
MCF5272 ColdFire
Signal Name
Table 14-1. QSPI Input and Output Signals and Functions
®
Integrated Microprocessor User’s Manual, Rev. 3
Configurable
N/A
Actively driven
Actively driven
Hi-Z or Actively Driven
Queued Serial Peripheral Interface (QSPI) Module
Serial data output from QSPI
Serial data input to QSPI
Clock output from QSPI
Peripheral selects
Function
14-3
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