MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 349
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Figure 14-5
14.5.2
Figure 14-6
Table 14-4
Freescale Semiconductor
14–8
Bits
7–0
15
Address
Reset
Field
R/W
Name
QCD
SPE
DTL
gives QDLYR field descriptions.
SPE
QSPI Delay Register (QDLYR)
shows the timing of the four SPI modes.
shows the QSPI delay register.
15
SCK
SCK
SCK
SCK
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the
command RAM. Automatically cleared by the QSPI when a transfer completes.The user can also clear this
bit to abort transfer unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set
QWR[HALT].
QSPILCK Delay. When the DSCK bit in the command RAM, is set this field determines the length of the
delay from assertion of the chip selects to valid QSPI_CLK transition.
after the serial transfer.
Delay after transfer.When the DT bit in the command RAM sets this field determines the length of delay
14
(CPOL = 1, CPHA = 1)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 0, CPHA = 0)
MCF5272 ColdFire
Figure 14-6. QSPI Delay Register (QDLYR)
Table 14-4. QDLYR Field Descriptions
QCD
Figure 14-5. SPI Modes Timing
®
Integrated Microprocessor User’s Manual, Rev. 3
0000_0100_0000_0100
MBAR + 0x00A4
R/W
8
Description
7
Queued Serial Peripheral Interface (QSPI) Module
DTL
0
14-11
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