MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 450

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Bus Operation
20.2.1
These output signals provide the location of a bus transfer. The address can be external SRAM, ROM,
FLASH, SDRAM, or peripherals.
20.2.2
These three-state bidirectional signals provide the general-purpose data path between the MCF5272 and
all other devices. The data bus can transfer 8, 16, 32, or 128 bits of data per bus transfer. The MCF5272
can be configured for an external physical data bus of 32- or 16-bits width. When configured for 16-bit
external data bus width, D[15:0] become GPIO port C. A write cycle drives all 32 or 16 bits of the data
bus regardless of the chip select port width and operand size.
20.2.3
This output signal defines the data transfer direction for the current bus cycle. A high (logic one) level
indicates a read cycle; a low (logic zero) level indicates a write cycle. During SDRAM bus cycles R/W is
driven high. When the CPU is in SLEEP or STOP modes, this signal is driven high.
20.2.4
This active-low synchronous input signal indicates the successful completion of a requested data transfer
operation. During MCF5272-initiated transfers, transfer acknowledge (TA) is an asynchronous input
signal from the referenced slave device indicating completion of the transfer.
The MCF5272 edge-detects and retimes the TA input. This means that an additional wait state may or may
not be inserted. For example if the active chip select is used to immediately generate the TA input, one or
two wait states may be inserted in the bus access.
The TA signal function is not available after reset. It must be enabled by configuring the appropriate pin
configuration register bits along with the value of CSORn[WS]. If TA is not used, it should either have a
pullup resistor or be driven through gating logic that always ensures the input is inactive. TA should be
negated on the negating edge of the active chip select.
20-2
Address Bus (A[22:0])
Data Bus (D[31:0])
Read/Write (R/W)
Transfer Acknowledge (TA)
The ColdFire core outputs 32 bits of address to the internal bus controller.
Of these 32 bits, only A[22:0] are output to pins on the MCF5272.
Use the OE signal to control any external data bus transceivers. In systems
containing numerous external peripherals, the chip selects should be used to
qualify any external transceivers. This ensures the transceivers are active
only when the desired peripheral is accessed. Using only the R/W signal to
control an external transceiver may lead to data bus conflicts in some system
architectures.
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
NOTE
Freescale Semiconductor