MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 148

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Debug Support
5.5.3.3.8
NOP
Command Formats:
Command Sequence:
Operand Data:
Result Data:
5.5.3.3.9
Read the selected control register and return the 32-bit result. Accesses to the processor/memory control
registers are always 32 bits wide, regardless of register width. The second and third words of the command
form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified
control register. The 12-bit Rc field is the same as that used by the MOVEC instruction.
Command/Result Formats:
Rc encoding:
5-30
performs no operation and may be used as a null command where required.
15
Command
Result
0x002
0x004
0x005
0x801
0x804
0x805
Rc
0x0
No Operation (
Read Control Register (
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Vector base register (VBR)
MAC status register (MACSR)
MAC mask register (MASK)
15
MCF5272 ColdFire
12
None
The command-complete response, 0xFFFF (with S cleared), is returned during the
next shift operation.
Register Definition
0x2
0x0
0x0
11
Figure 5-33.
NOP
12
Figure 5-32.
Figure 5-31.
Table 5-19. Control Register Map
)
®
11
0x0
Integrated Microprocessor User’s Manual, Rev. 3
NOP
???
RCREG
RCREG
0x9
0x0
NOP
NOP
Command/Result Formats
8
)
Command Sequence
Command Format
D[31:16]
0x80E
0xC04
0xC0F
0x806
0x80F
"CMD COMPLETE"
8
D[15:0]
7
Rc
NEXT CMD
7
MAC accumulator (ACC)
Status register (SR)
Program register (PC)
RAM base address register (RAMBAR)
Module base address (MBAR)
0x0
0x8
0x0
Rc
Register Definition
4
4
3
3
Freescale Semiconductor
0x0
0x0
0x0
0
0