MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 304

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Physical Layer Interface Controller (PLIC)
13.2.3.5
Typically, when the CPU wants to transmit a D-channel packet, it starts the HDLC framer.
In IDL mode, when the CPU can start sending data from the prepared HDLC frame to the D-channel
transmit register, it asserts DREQ by setting the appropriate DRQ bit in the PDRQR register. The
D-channel controller hardware looks for a valid DGRANT back from the layer 1 transceiver and, assuming
DREQ is also valid, begins transmitting the D-channel packet. PDCSR[DGn] reflects the value of the
dedicated DGRANT pin. Refer to the MC145574 data sheet for SCIT mode information.
In GCI mode the only D-channel contention control is provided by PnCR[G/S],
Configuration Registers
Section 13.5.19, “D-Channel Status Register
to control D-channel transmission along with PDRQR[DRQn],
Register
such as the indirect mode found on the Freescale MC145574. In GCI mode, the DGRANT pin function
found in IDL mode is disabled and the pin can be defined for other functions. Please note that the
D-channel periodic interrupts in both the receive and transmit direction are not disabled even though the
shift register is disabled by DREQ, DGRANT, and PDRQR[DCNTIn]
Request Register
An override mechanism for D-channel contention control is provided through the D-channel ignore
DCNTI bit.
Figure 13-8
13.2.4
The PLIC ports can be configured to operate in various looping modes as shown in
modes are useful for local and remote system diagnostic functions.
The loopback modes are independent signal loopbacks for the respective ports. These loopbacks allow for
the echoing of local or remote information. In auto-echo or remote-loopback modes there is no time
switching or time slot assignment function. All data received on Din is transmitted on Dout during the
same time slot. Similarly, in local-loopback mode, the information transmitted on the Dout pin is echoed
back on Din during the same time slot.
The PLIC transmitter and receiver should both be disabled when switching between modes.
13-8
(PDRQR).” In GCI mode, the PLIC ports do not support any other form of D-channel contention
GCI/IDL Looping Modes
illustrates this functionality:
GCI/IDL D-Channel Contention
(PDRQR)”) configuration.
MCF5272 ColdFire
(P0CR–P3CR).” Provided the PLIC operates in SCIT mode, PDCSR[DGn],
Figure 13-8. D-Channel Contention
®
Integrated Microprocessor User’s Manual, Rev. 3
Shift Register Enable
(PDCSR),” is defined by the state of PnCR[G/S], and is used
Section 13.5.20, “D-Channel Request
(Section 13.5.20, “D-Channel
DGRANT
DREQ
DCNTI
Section 13.5.7, “Port
Figure
Freescale Semiconductor
13-9. These