MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 354
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Serial Peripheral Interface (QSPI) Module
14.5.8
The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of 4.125 MHz.
The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example.
14-16
1. Enable all QSPI_CS pins on the MCF5272. Write PACNT with 0x0080_4000 to enable QSPI_CS1
2. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling clock
3. Write QDLYR with the desired delays.
4. Write QIR with 0xD00D to enable write collision, abort bus errors, and clear any interrupts.
5. Write QAR with 0x0020 to select the first command RAM entry.
6. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00, 0x7B00,
7. Write QAR with 0x0000 to select the first transmit RAM entry.
8. Write QDR with sixteen 12-bit words of data.
9. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15.
10. Set QDLYR[SPE] to enable the transfers.
11. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete.
12. Write QAR with 0x0010 to select the first receive RAM entry.
13. Read QDR to get the received data for each transfer.
14. Repeat steps 5 through 13 to do another transfer.
and QSPI_CS3.Write PDCNT with 0x0000_0030 to enable QSPI_CS2.
edge, and a clock frequency of 4.125 MHz (assuming a 66-MHz CLKIN).
0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each
chip select. The chip selects are active low in this example.
Programming Example
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
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