MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 222

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Ethernet Module
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5272
configuration for seven-wire serial mode connections to the external transceiver are shown in
11.4
Figure 11-3
The Ethernet transmitter is designed to work with almost no host intervention. As soon as the driver
enables the FEC transmitter by setting ECR[ETHER_EN] and TDAR[24], the FEC fetches the first
transmit buffer descriptor (TxBD). If the user has a frame ready to transmit, DMA of the transmit data
buffer(s) begins immediately. A collision window (512 bits) of transmit data is sent as a DMA to the
transmit FIFO before off-chip transmission begins.
When the transmit FIFO contains 512 bits of data, the FEC asserts E_TxEN and starts transmitting the
preamble sequence, the start-of-frame delimiter, and then the frame data. However, if the line is busy, the
controller defers the transmission (carrier sense is active). Before transmitting, the controller waits for
carrier sense to become inactive. When carrier sense goes inactive, the controller waits to verify that it
11-4
NOTE: Short Tx frames are padded automatically by the MCF5272
FEC Frame Transmission
Preamble
7 Bytes
shows the Ethernet frame format.
Start Frame
Delimiter
MCF5272 ColdFire
1 Byte
Transmit clock
Transmit enable
Transmit data
Collision
Receive clock
Receive enable
Receive data
Unused, configure as PB14
Unused input, tie to ground
Unused, configure as PB[13:11]
Unused output, ignore
Unused, configure as PB[10:8]
Unused, configure as PB15
Input after reset, connect to ground
Table 11-2. Seven-Wire Mode Configuration
Destination
Address
6 Bytes
Figure 11-3. Ethernet Frame Format
Signal Description
®
Integrated Microprocessor User’s Manual, Rev. 3
Address
6 Bytes
Source
Stored in Transmit Buffer
Stored in Receive Buffer
2 Bytes
Length
Type/
E_TxCLK
E_COL
E_RxCLK
E_CRS
E_RxD[3:1]
E_TxER
E_MDC
E_MDIO
E_TxEN
E_TxD[0]
E_RxDV
E_RxD[0]
E_RxER
E_TxD[3:1]
MCF5272 Pin
46–1500 Bytes
Data
(Pads)
Freescale Semiconductor
Frame Check
Sequence
4 Bytes
Table
11-2.