MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 40
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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About This Book
The primary objective of this user’s manual is to define the functionality of the MCF5272 processors for
use by software and hardware developers.
The information in this book is subject to change without notice, as described in the disclaimers on the title
page of this book. As with any technical documentation, it is the readers’ responsibility to be sure he is
using the most recent version of the documentation.
To locate any published errata or updates for this document, refer to the world-wide web at
http://www.freescale.com.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with the MCF5272. It is assumed that the reader understands operating systems,
microprocessor system design, basic principles of software and hardware, and basic details of the
ColdFire
Organization
Following is a summary and brief description of the major sections of this manual:
xl
•
•
•
•
Chapter 1,
the MCF5272, focussing in particular on new features.
Chapter 2, “ColdFire
The chapter describes the organization of the Version 2 (V2) ColdFire 5200 processor core and an
overview of the program-visible registers (the programming model) as they are implemented on
the MCF5272. It also includes a full description of exception handling and a table of instruction
timings.
Chapter 3, “Hardware Multiply/Accumulate (MAC)
multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and
miscellaneous register instructions. The MAC is integrated into the operand execution pipeline
(OEP).
Chapter 4, “Local
V2 local memory specification. It consists of three major sections, as follows.
—
—
—
®
architecture.
Section 4.3, “SRAM
implementation. It covers general operations, configuration, and initialization. It also provides
information and examples of how to minimize power consumption when using the SRAM.
Section 4.4, “ROM
module contains tabular data that the ColdFire core can access in a single cycle.
Section 4.5, “Instruction Cache
including organization, configuration, and coherency. It describes cache operations and how
the cache interacts with other memory structures.
“Overview,” includes general descriptions of the modules and features incorporated in
MCF5272 ColdFire
Memory.” This chapter describes the MCF5272 implementation of the ColdFire
Core,” provides an overview of the microprocessor core of the MCF5272.
Overview,” describes the MCF5272 on-chip static ROM. The ROM
Overview,” describes the MCF5272 on-chip static RAM (SRAM)
®
Integrated Microprocessor User’s Manual, Rev. 3
Overview,” describes the MCF5272 cache implementation,
Unit,” describes the MCF5272
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