MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 169

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Table 6-6
Freescale Semiconductor
PDN
Bits
7-6
3-0
0
1
1
10
9
8
5
4
WK
X
0
1
UART1WK
UART0WK
details the interaction between the PDN and WK bits for the USB and USART modules.
USBWK
SLPEN
Field
MOS
Module powered up and operating normally.
Module in power down and can only be reactivated by clearing PDN.
Module in power down and can be reactivated by clearing PDN or detecting signal on the receive pins.
—
—
USB wakeup enable. Allows clocking to the USB module to be restored when a change in signal level
is detected on USD_D+ or INT1/USB_WOR. See
the PDN and WK bits.
0 Wakeup disabled.
1 Wakeup enabled. USBPDN must also be set.
UART1 wakeup enable. Allows clocking to the UART1 module to be restored when a change in signal
level is detected on UART1RxD. See
WK bits.
0 Wakeup disabled.
1 Wakeup enabled. UART1PDN must also be set.
UART0 wakeup enable. Allows clocking to the UART0 module to be restored when a change in signal
level is detected on UART0RxD. See
WK bits.
0 Wakeup disabled.
1 Wakeup enabled. UART0PDN must also be set.
Reserved, should be cleared.
Main oscillator stop. Allows the MCF5272 to be put into stop mode, in which internal clocking is stopped
to the entire processor. To enter stop mode, the user must write to the ALPR and then execute a STOP
instruction. See
on-chip modules in power down mode. After setting this bit, a write access must be made to the ALPR
register to actually enter stop mode. D[31:0] are driven low, and other bus signals are negated. Stop
mode is exited when an interrupt is detected on one the external interrupt pins, INT[6:1].
0 Stop mode disabled.
1 Stop mode enabled.
Sleep enable. Allows the MCF5272 to be put into sleep mode in which internal clocking to the CPU is
disabled.To enter sleep mode, the user must write to the ALPR and then execute a STOP instruction.
See
disabled through the appropriate PDN bits. After SLPEN is set, a write access must be made to ALPR
to actually enter sleep mode. D[31:0] are driven low, and other bus signals are negated. Sleep mode is
exited when an interrupt is detected from an on-chip peripheral or one of the external interrupt pins,
INT[6:1].
0 Sleep mode disabled.
1 Sleep mode enabled.
Reserved, should be cleared.
MCF5272 ColdFire
Section 6.2.6, “Activate Low-Power Register
Table 6-6. USB and USART Power Down Modes
Table 6-5. PMR Field Descriptions (continued)
Section 6.2.6, “Activate Low-Power Register
®
Integrated Microprocessor User’s Manual, Rev. 3
Table 6-6
Table 6-6
Description
Description
for a description of the interaction between the PDN and
for a description of the interaction between the PDN and
Table 6-6
(ALPR).” Individual modules may have clocking
for a description of the interaction between
(ALPR).” It is not necessary to put any
System Integration Module (SIM)
6-9