MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 187

• Manufacturer Part Number: MCF5272CVF66J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Leaded Process Compatible: No
• Rohs Compliant: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

8.2.1
The CSBRs,
determine whether a specific chip select should assert. A bus cycle in a specific chip select register causes
the assertion of the corresponding external chip select.
Table 8-2
Freescale Semiconductor
31–12
11–10
Bits
9–8
6–5
7
Reset
Field
Addr
R/W
SUPER
31
Name
describes CSBRn fields.
EBI
BW
BA
TT
Chip Select Base Registers (CSBR0–CSBR7)
Figure
CSBR0: 0x0000_0x01
CSBR4: 0x0000_4300; CSBR5: 0x0000_5300; CSBR6: 0x0000_6300; CSBR7: 0x0000_7700
Base address. The starting address of the memory space covered by the chip select. BA is compared with
bits 31–12 of the access to determine whether the current bus cycle is intended for this chip select. Any
combination of BA bits can be masked in the associated CSOR.
External bus interface modes. These modes are used to multiplex outputs and determine timing of the
appropriate bus interface module onto the device pins.
00 16-/32-bit SRAM/ROM. For 16-/32-bit wide memory devices with byte strobe inputs. CSBR0[EBI] = 00
01 SDRAM. One physical bank of SDRAM consisting of 16–256 Mbit devices. CSOR7[WS] must be set
10 Reserved
11 Use SRAM/ROM timing for 8-bit devices without byte strobe inputs.
Bus width. Determines data bus size of the memory-mapped resource for all chip selects except CS0. It
is assumed that boot code for the processor is accessed through the global chip select CS0, so the initial
bus width for this chip select must be configured at reset. QSPI_CS0/BUSW0 and QSPI_CLK/BUSW1 are
used to program the bus width for CS0 at reset.
00 Longword (32 bits)
01 Byte (8 bits)
10 Word (16 bits)
11 Cache line (32 bits)
Supervisor mode.
0 Bus cycle may be in user or supervisor mode (neglecting conditions imposed by setting CTM).
1 The chip select asserts a match only if the transfer modifier indicates a supervisor mode access. A user
SUPER, CTM, TT, and TM are used to restrict bus access. For example, if TT and TM indicate a user data
access and SUPER and CTM are both set, no accesses can occur.
Transfer type. TT and TM may be used to further qualify the address match. If CTM is set, TT and TM must
match the access types for the chip select to assert. See the description of TM.
8-1, provide a model internal bus cycle against which to match actual bus cycles to
access matching BA causes an access error.
at reset. Affects all chip selects.
to 0x1F. Affects only CS7/SDCS.
BA
MCF5272 ColdFire
0x040 (CSBR0); 0x048 (CSBR1); 0x050 (CSBR2); 0x058 (CSBR3);
0x060 (CSBR4); 0x068 (CSBR5); 0x070 (CSBR6); 0x078 (CSBR7)
Figure 8-1. Chip Select Base Registers (CSBRn)
12 11
1
Table 8-2. CSBRn Field Descriptions
; CSBR1: 0x0000_1300; CSBR2: 0x0000_2300; CSBR3: 0x0000_3300;
®
EBI
Integrated Microprocessor User’s Manual, Rev. 3
10
9
BW
8
SUPER
R/W
Description
7
6
TT
5
4
TM
2
CTM ENABLE
1
Chip Select Module
0
8-3