MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 344
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Serial Peripheral Interface (QSPI) Module
14.4.1.2
Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF.
The user normally writes 1 word into this segment for each queue command to be executed. The user
cannot read transmit RAM.
Out-bound data must be written to transmit RAM in a right-justified format. The unused bits are ignored.
The QSPI copies the data to its data serializer (shift register) for transmission. The data is transmitted most
significant bit first and remains in transmit RAM until overwritten by the user.
14.4.1.3
The CPU writes one byte of control information to this segment for each QSPI command to be executed.
Command RAM is write-only memory from a user’s perspective.
Command RAM consists of 16 bytes with each byte divided into two fields. The peripheral chip select
field controls the QSPI_CS signal levels for the transfer. The command control field provides transfer
options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in
QWR[NEWQP] through the address in QWR[ENDQP].
The QSPI executes a queue of commands defined by the control bits in each command RAM entry which
sequence the following actions:
Before any data transfers begin, control data must be written to the command RAM, and any out-bound
data must be written to transmit RAM. Also, the queue pointers must be initialized to the first and last
entries in the command queue.
Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity are
controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which QSPI_CLK edge is
used to drive outgoing data and to latch incoming data.
14.4.2
The maximum QSPI clock frequency is one-fourth the clock frequency applied at the CLKIN pin. Baud
rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the
QSPI_CLK rate from the system clock, CLKIN, divided by two.
A baud rate value of zero turns off the QSPI_CLK. The desired QSPI_CLK baud rate is related to CLKIN
and QMR[BAUD] by the following expression:
QMR[BAUD] = CLKIN / [2 × (desired QSPI_CLK baud rate)]
14-6
•
•
•
chip-select pins are activated
data is transmitted from transmit RAM and received into the receive RAM
the synchronous transfer clock QSPI_CLK is generated
Baud Rate Selection
Transmit RAM
Command RAM
MCF5272 ColdFire
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
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