MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 198
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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SDRAM Controller
9.5.2
The SDTR is used to configure SDRAM controller refresh counters for the type of SDRAM devices used
and the number of clocks required for each type of SDRAM access. The reset value is 0x2115. For lower
CPU clock frequencies, precharge and activate times can be reduced to eliminate up to 2 clock cycles from
the read and write accesses. Consult the data sheets of the SDRAMs being considered.
Table 9-8
9-8
15–10
Bits
9–8
7–6
5–4
Reset
Write
Addr
R/W
Name
RTP
describes SDTR fields.
RC
RP
—
SDRAM Timing Register (SDTR)
15
Refresh timer prescaler. Determines the number of clock cycles x 16 between refreshes. The following table
describes different recommended prescaler settings for different clock frequencies including a margin of 1.2
μS. Recommended values are as follows:
Refresh count. Indicates the number of clock cycles spent in refresh state (RC + 5). Refresh occurs during
the first of these clock cycles; the rest of the time is the delay that must occur before the SDRAM is ready
to do anything else.
00 5 cycles
01 6 cycles (default)
10 7 cycles
11 8 cycles
Reserved, should be cleared.
Precharge time. Specifies number of clock cycles taken for a precharge (RP + 1).
00 1 cycle
01 2 cycles (default)
10 3 cycles
11 4 cycles
MCF5272 ColdFire
0010_00
RTP
111101
101011
011101
010110
000100
Figure 9-4. SDRAM Timing Register (SDTR)
RTP
Table 9-8. SDTR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
10
15.6 µs = 1/f*RTP*16
9
RC
MBAR + 0x0186
01
8
61
43
29
22
R/W
4
Description
7
—
00
6
5 MHz (emulator)
5
System Clock
RP
01
66 MHz
48 MHz
33 MHz
25 MHz
4
3
RCD
01
Freescale Semiconductor
2
1
CLT
01
0
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