MCF5272CVF66J Freescale Semiconductor, MCF5272CVF66J Datasheet - Page 76
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MCF5272CVF66J
Manufacturer Part Number
MCF5272CVF66J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Leaded Process Compatible
No
Rohs Compliant
No
Peak Reflow Compatible (260 C)
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Core
2.2.2.1
The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software
can read or write the entire SR; user software can read or write only SR[7–0], described in
“Condition Code Register
or user mode (S), and master or interrupt state (M). SR is set to 0x27xx after reset.
Table 2-3
2.2.2.2
The VBR holds the base address of the exception vector table in memory. The displacement of an
exception vector is added to the value in this register to access the vector table. VBR[19–0] are not
implemented and are assumed to be zero, forcing the vector table to be aligned on a 0-modulo-1-Mbyte
boundary.
2-8
Rc[11–0]
Reset
10–8
Field
Bits
7–0
R/W R/W
15
13
12
Reset
Field
R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from
describes SR fields.
Name
15
T
0
CCR
31
M
S
Status Register (SR)
T
Vector Base Register (VBR)
Exception vector table base address
I
—
R
0
Trace enable. When T is set, the processor performs a trace exception after every instruction.
Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution
of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.
Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited for all
priority levels less than or equal to the current priority, except the edge-sensitive level-7 request,
which cannot be masked.
Condition code register. See
the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined.
MCF5272 ColdFire
R/W
S
1
(CCR).” The control bits indicate processor states—trace mode (T), supervisor
System Byte
R/W
M
0
Figure 2-6. Vector Base Register (VBR)
—
R
0
0000_0000_0000_0000_0000_0000_0000_0000
Figure 2-5. Status Register (SR)
Table 2-3. Status Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
Figure
20 19
R/W
111
I
2-4.
8
Description
0x801
7
000
—
R
Condition Code Register (CCR)
—
R/W
—
X
R/W
—
N
Freescale Semiconductor
R/W
—
Z
Section 2.2.1.5,
R/W
—
V
R/W
—
C
0
0
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