HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 122

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.2
WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals
supplied to the supporting modules. It also controls wait state controller wait settings, RAM area
setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply
flash memory control registers.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Notes: *1 These bits are valid only in the H8/3437F and H8/3434F (dual-power-supply on-chip
Bit 7—RAM Select (RAMS)
Bit 6—RAM Area Select (RAM0)
Bits 7 and 6 select a RAM area for emulation of dual-power-supply flash memory updates. For
details, see the flash memory description in section 19, 20, ROM.
Bit 5—Clock Double (CKDBL): Controls the frequency division of clock signals supplied to
supporting modules.
Bit 5: CKDBL
0
1
Bit 4—Flash Memory Control Register Enable (FLSHE): Controls selection/non-selection of
single-power-supply flash memory control registers. For details, see the description of flash
memory in section 21, ROM. In models other than the H8/3437SF, this bit is reserved, but it can
be written and read; its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0)
These bits control wait-state insertion. For details, see section 5, Wait-State Controller.
90
Bit
Initial value
Read/Write
*2 This bit is valid only in the H8/3437SF (S-mask model, single-power-supply on-chip
Wait-State Control Register (WSCR)
flash memory versions).
flash memory version).
RAMS
R/W
Description
The undivided system clock (ø) is supplied as the clock (ø
modules.
The system clock (ø) is divided by two and supplied as the clock (ø
supporting modules.
7
0
*1
RAM0
R/W
6
0
*1
CKDBL FLSHE
R/W
5
0
R/W
4
0
*2
WMS1
R/W
3
1
WMS0
R/W
2
0
P
) for supporting
WC1
R/W
1
0
(Initial value)
P
) for
WC0
R/W
0
0