HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 647

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HD64F3437TFI16V

Manufacturer Part Number
HD64F3437TFI16V
Description
MCU FLASH 60K 100-TQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F3437TFI16V

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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A.3
The tables below can be used to calculate the number of states required for instruction execution.
Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates
the number of cycles of each type occurring in each instruction. The total number of states
required for execution of an instruction can be calculated from these two tables as follows:
Execution states = I
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
2. JSR @@30
Table A.3
Execution Status
(Instruction Cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Notes: m: Number of wait states inserted in access to external device.
From table A.4: I = L = 2,
From table A.3: S
Number of states required for execution: 2
From table A.4: I = 2,
From table A.3: S
Number of states required for execution: 2
Number of States Required for Execution
Number of States Taken by Each Cycle in Instruction Execution
I
I
S
= 8,
= S
I
S
S
S
S
S
S
+ J S
I
J
K
L
M
N
J
= S
J = K = 1,
S
K
L
J
= 8
+ K S
= 3
On-Chip Memory
2
1
J = K = M = N= 0
K
L = M = N = 0
+ L S
8 + 2 3 =22
8 + 1 8 + 1 8 = 32
L
+ M S
On-Chip Reg. Field
6
3
6
1
Access Location
M
+ N S
N
External Memory
6 + 2m
3 + m
6 + 2m
1
615

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