HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 544

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HD64F3437TFI16V

Manufacturer Part Number
HD64F3437TFI16V
Description
MCU FLASH 60K 100-TQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F3437TFI16V

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 21.5 Flash Memory Erase Blocks
Block (Size)
60-Kbyte Version
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (16 kbytes)
EB6 (12 kbytes)
EB7 (2 kbytes)
21.2.4
WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals
supplied to the supporting modules. It also controls wait state controller wait settings, RAM area
setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply
flash memory control registers.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Reserved: These bits are reserved, but can be written and read. Their initial value
is 0.
Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to the on-
chip supporting modules. For details, see section 6, Clock Pulse Generator.
512
Bit
Initial value
Read/Write
Wait-State Control Register (WSCR)
R/W
7
0
R/W
6
0
Addresses
H'0000–H'03FF
H'0400–H'07FF
H'0800–H'0BFF
H'0C00–H'0FFF
H'1000–H'7FFF
H'8000–H'BFFF
H'C000–H'EF7F
H'EF80–H'F77F
CKDBL
R/W
5
0
FLSHE
R/W
4
0
WMS1
R/W
3
1
WMS0
R/W
2
0
WC1
R/W
1
0
WC0
R/W
0
0

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