HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 337

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HD64F3437TFI16V

Manufacturer Part Number
HD64F3437TFI16V
Description
MCU FLASH 60K 100-TQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F3437TFI16V

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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13.3.6
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR and
ACK bit in ICCR. SCL is automatically held low after one frame has been transferred; this timing
is synchronized with the internal clock. Figure 13.10 shows the IRIC set timing and SCL control.
(a) When WAIT = 0 and ACK = 0
(b) When WAIT = 1 and ACK = 0
(c) When ACK = 1
IRIC Set Timing and SCL Control
SCL
SDA
IRIC
User processing
Note: The ICDR write (transmit) or read (receive) following the clearing of IRIC
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
should be executed after the rise of SCL (ninth clock pulse).
7
7
7
Figure 13.10 IRIC Set Timing and SCL Control
8
8
8
Clear IRIC
Clear IRIC
Clear IRIC
A
A
Write to ICDR (transmit)
or read ICDR (receive)
Write to ICDR (transmit)
or read ICDR (receive)
Write to ICDR (transmit)
or read ICDR (receive)
1
1
1
305

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