HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 346

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HD64F3437TFI16V

Manufacturer Part Number
HD64F3437TFI16V
Description
MCU FLASH 60K 100-TQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F3437TFI16V

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Countermeasure
Figure 13.19 shows the recommended program flow.
Additional Note
When switching from master receive mode to master transmit mode, ensure that TRS is set to 1
before the last receive data is latched by reading ICDR.
Precautions when Clearing the IRIC Flag when Using the Wait Function
If the SCL rise time exceeds the specified duration when using the wait function in the I
interface’s master mode, or if there is a slave device that keeps SCL low and applies a wait
state, read SCL and clear the IRIC flag only after determining that SCL has gone low, as
shown below.
If the IRIC flag is cleared to 0 when WAIT is set to 1 and while the SCL high level duration is
being extended, the SDA value may change before SCL falls, erroneously resulting in a start or
stop condition.
Write data to ICDR
data present?
Transmit
Figure 13.19 Recommended Program Flow
Yes
No
No
No
No
Write 0 to BBSY and
Read ACKB in ICSR
Read IRIC in ICSR
0 to SCP in ICSR
ACKB = 1?
Read SCL
IRIC = 1?
SCL = 0?
Yes
Yes
Yes
2
C bus

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