HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 555

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.4.3
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 21.13.
The wait times (x, y, z, , ,
registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erases (N), see Flash
Memory Characteristics in section 23, Electrical Characteristics.
To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in
erase block register 2 (EBR2) at least (x) s after setting the SWE bit to 1 in flash memory control
register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of
program runaway, etc. Set a value greater than (y + z +
After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in
FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to erase mode by
setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase
time. Ensure that the erase time does not exceed (z) ms.
Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased
21.4.4
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the
ESU bit in FLMCR2 is cleared at least ( ) s later), the watchdog timer is cleared after the elapse
of ( ) s or more, and the operating mode is switched to erase-verify mode by setting the EV bit in
FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of ( ) s or more.
When the flash memory is read in this state (verify data is read in 16-bit units), the data at the
latched address is read. Wait at least ( ) s after the dummy write before performing this read
operation. If the read data has been erased (all 1), a dummy write is performed to the next address,
and erase-verify is performed. If the read data has not been erased, set erase mode again, and
repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-
verify sequence is not repeated more than (N) times. When verification is completed, exit erase-
verify mode, and wait for at least ( ) s. If erasure has been completed on all the erase blocks,
clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting in EBR2 for
the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way.
to 0) is not necessary before starting the erase procedure.
Erase Mode
Erase-Verify Mode
after setting/clearing individual bits in flash memory control
+ ) ms as the WDT overflow period.
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