HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 126
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HD64F3437TFI16V
Manufacturer Part Number
HD64F3437TFI16V
Description
MCU FLASH 60K 100-TQFP
Manufacturer
Renesas Electronics America
Datasheet
1.HD64F3437TFI16V.pdf
(755 pages)
Specifications of HD64F3437TFI16V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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External Clock Input: The external clock signal should have the same frequency as the desired
system clock (ø). Clock timing parameters are given in table 6.3 and figure 6.6.
Table 6.3
Item
Low pulse
width of external
clock input
High pulse
width of external
clock input
External clock
rise time
External clock
fall time
Clock pulse
width low
Clock pulse
width high
Table 6.4 lists the external clock output stabilization delay time. Figure 6.7 shows the timing for
the external clock output stabilization delay time. The oscillator and duty correction circuit have
the function of regulating the waveform of the external clock input to the EXTAL pin. When the
specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after
the elapse of the external clock output stabilization delay time (t
confirmed during the t
maintained during this time.
94
EXTAL
Clock Timing
Symbol
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
DEXT
period, the reset signal should be driven low and the reset state
Figure 6.6 External Clock Input Timing
V
5.5 V
Min
40
40
—
—
0.3
0.4
0.3
0.4
CC
= 2.7 to
t
EXr
Max
—
—
10
10
0.7
0.6
0.7
0.6
t
EXH
V
5.5 V
Min
30
30
—
—
0.3
0.4
0.3
0.4
CC
= 4.0 to
Max
—
—
10
10
0.7
0.6
0.7
0.6
V
Min
20
20
—
—
0.3
0.4
0.3
0.4
t
EXt
10%
CC
= 5.0 V
DEXT
Max
—
—
5
5
0.7
0.6
0.7
0.6
t
EXL
). As clock signal output is not
Unit Test Conditions
ns
ns
ns
ns
t
t
t
t
cyc
cyc
cyc
cyc
Figure 6.6
ø
ø < 5 MHz 23.7
ø
ø < 5 MHz
V
5 MHz Figure
5 MHz
CC
0.5
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