HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 698

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ICSR—I
666
Note: * Only 0 can be written, to clear the flag.
Bit
Initial value
Read/Write
Bus Busy
0
1
Bus is free
Cleared by detection
of a stop condition
Bus is busy
Set by detection
of a start condition
Start Condition/Stop Condition Prohibit
0
1
2
Arbitration Lost Flag
C Bus Status Register
0
1
Writing 0 issues a start or stop condition, in combination with BBSY
Reading always results in 1
Writing is ignored
Slave Address Recognition Flag
0
1
Bus arbitration won
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading AL = 1, then writing 0
Arbitration lost
Set if the internal SDA and bus line disagree at the rise of SCL in master transmit mode
Set if the internal SCL is high at the fall of SCL in master transmit mode
General Call Address Recognition Flag
0
1
Slave address or general call address not recognized (Initial value)
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading AAS = 1, then writing 0
Slave address or general call address recognized
Set when the slave address or general call address is detected in slave receive mode
General call address not recognized
Cleared when ICDR data is written (transmit mode) or read (receive mode)
Cleared by reading ADZ = 1, then writing 0
General call address recognized
Set when the general call address is detected in slave receive mode
Acknowledge Bit
BBSY
0
1
R/W
7
0
Receive mode: 0 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has acknowledged the data
Receive mode: 1 is output at acknowledge output timing
Transmit mode: indicates that the receiving device has not acknowledged the data
I
2
0
1
C Bus Interface Interrupt Request Flag
Waiting for transfer, or transfer in progress
Cleared by reading IRIC = 1, then writing 0
Interrupt requested
Set to 1 at the following times:
Master mode
• End of data transfer
• Bus arbitration lost
Slave mode (when FS = 0)
• When the slave address is matched, and whenever a data transfer ends at timing of
• When a general call address is detected, and whenever a data transfer ends at timing
Slave mode (when FS = 1)
• End of data transfer
a retransmit start condition after address matching or a stop condition is detected
of a retransmit start condition after address detection or a stop condition is detected
R/(W)*
IRIC
6
0
SCP
W
5
1
—
—
4
1
R/(W)*
AL
3
0
H'D9
R/(W)*
AAS
2
0
R/(W)*
ADZ
1
0
ACKB
R/W
0
0
I
2
C