S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 254

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

S12XE Clocks and Reset Generator (S12XECRGV1)
8.4.1.2
The clock generator creates the clocks used in the MCU (see
top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.
The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see
to PLLCLK running at its minimum frequency f
the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus Clock. But
note that a CPU cycle corresponds to one Bus Clock.
IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output clock
drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned off by
clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a maximum of 4
OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU
activity ceases.
254
EXTAL
XTAL
Condition
OSCILLATOR
Gating
System Clocks Generator
LOOP (IIPLL)
= Clock Gate
PHASE
LOCK
OSCCLK
PLLCLK
Monitor
Clock
S12XS Family Reference Manual, Rev. 1.11
Figure 8-16. System Clocks Generator
Section 8.4.2.2, “Self Clock
PLLSEL or SCM
1
0
1
0
SCM
SCM
STOP(PSTP, PCE),
STOP(PSTP, PRE),
WAIT(COPWAI),
WAIT(RTIWAI),
COP ENABLE
RTI ENABLE
. The Bus Clock is used to generate the clock visible at
SYSCLK
STOP
Figure
STOP
Mode”) Oscillator clock source is switched
8-16). The gating condition placed on
÷2
CLOCK PHASE
GENERATOR
COP
RTI
Freescale Semiconductor
Core Clock
Bus Clock
Oscillator
Clock