S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 52

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Overview S12XS Family
I-bit maskable service request is a configuration register. It selects if the service request is enabled and the
service request priority level.
52
Vector base + $CC
Vector base + $EC
Vector base + $DA
Vector base + $D8
Vector base + $D4
Vector base + $D2
Vector base + $D0
Vector base + $CE
Vector base + $CA
Vector base + $C8
Vector base + $C6
Vector base + $C4
Vector base + $C2
Vector base + $BC
Vector base + $F8
Vector base + $E2
Vector base+ $DC
Vector base+ $EE
Vector base+ $EA
Vector base+ $DE
Vector base+ $F6
Vector base+ $F4
Vector base+ $F2
Vector base+ $F0
Vector base+ $E8
Vector base+ $E6
Vector base+ $E4
Vector base+ $E0
Vector base+ $D6
Vector Address
to
1
TIM Pulse accumulator input edge
TIM Pulse accumulator A overflow
Unimplemented instruction trap
Table 1-10. Interrupt Vector Locations (Sheet 1 of 2)
CRG self-clock mode
TIM timer channel 0
TIM timer channel 1
TIM timer channel 2
TIM timer channel 3
TIM timer channel 4
TIM timer channel 5
TIM timer channel 6
TIM timer channel 7
Real time interrupt
TIM timer overflow
Interrupt Source
CRG PLL lock
S12XS Family Reference Manual, Rev. 1.11
Port H
Port J
XIRQ
ATD0
SCI0
SCI1
SPI0
SWI
IRQ
Mask
None
None
CCR
X Bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
Reserved
Reserved
Reserved
Reserved
SPI0CR1 (SPIE, SPTIE)
(TIE, TCIE, RIE, ILIE)
(TIE, TCIE, RIE, ILIE)
PIEH (PIEH7-PIEH0)
ATD0CTL2 (ASCIE)
PIEJ (PIEJ7-PIEJ0)
CRGINT(LOCKIE)
CRGINT (SCMIE)
IRQCR (IRQEN)
CRGINT (RTIE)
PACTL (PAOVI)
TSRC2 (TOF)
Local Enable
PACTL (PAI)
SCI0CR2
SCI1CR2
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
None
None
None
Freescale Semiconductor
Wake up
STOP
interrupt section
interrupt section
interrupt section
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Refer to CRG
No
No
No
No
No
No
No
No
No
No
No
No
Refer to CRG
Refer to CRG
—
—
Wake up
WAIT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—