S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 60

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Port Integration Module (S12XSPIMV1)
2.1.2
The Port Integration Module includes these distinctive registers:
A standard port pin has the following minimum features:
Optional features supported on dedicated pins:
2.2
This section lists and describes the signals that connect off-chip.
Table
the device definition for the availability of the individual pins in the different package options.
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Open drain for wired-or connections
Interrupt inputs with glitch filtering
shows all the pins and their functions that are controlled by the Port Integration Module. Refer to
Data and data direction registers for Ports A, B, E, K, T, S, M, P, H, J, and AD when used as
general-purpose I/O
Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,
H, and J on per-pin basis
Control registers to enable/disable pull-up devices on Port AD on per-pin basis
Single control register to enable/disable pull-ups on Ports A, B, E, and K on per-port basis and on
BKGD pin
Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, and AD on per-pin
basis
Single control register to enable/disable reduced output drive on Ports A, B, E, and K on per-port
basis
Control registers to enable/disable open-drain (wired-or) mode on Ports S, and M
Interrupt flag register for pin interrupts on Ports P, H, and J
Control register to configure IRQ pin operation
Routing registers to support module port relocation
Free-running clock outputs
Input/output selection
5V output drive with two selectable drive strengths
5V digital and analog input
Input with selectable pull-up or pull-down device
External Signal Description
Features
This document assumes the availability of all features (112-pin package
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary section.
S12XS Family Reference Manual, Rev. 1.11
NOTE
Freescale Semiconductor