S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 273

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S9S12XS256J0CAL

Manufacturer Part Number
S9S12XS256J0CAL
Description
MCU 256K FLASH 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of S9S12XS256J0CAL

Core Processor
HCS12X
Core Size
16-Bit
Speed
40MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
91
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
8K x 8
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12XS
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
91
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
DEMO9S12XSFAME, EVB9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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10.2
This section lists all inputs to the ADC12B16C block.
10.2.1
10.2.1.1
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
10.2.1.2
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connection of these inputs!
10.2.1.3
V
10.2.1.4
These pins are the power supplies for the analog circuitry of the ADC12B16C block.
10.3
This section provides a detailed description of all registers accessible in the ADC12B16C.
10.3.1
Figure 10-2
Freescale Semiconductor
Address
0x0000
0x0001
0x0002
RH
is the high reference voltage, V
Signal Description
Memory Map and Register Definition
ATDCTL0
ATDCTL1
ATDCTL2
Detailed Signal Descriptions
Module Memory Map
Name
gives an overview on all ADC12B16C registers.
ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
ETRIG3, ETRIG2, ETRIG1, ETRIG0
V
V
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
RH
DDA
, V
, V
W
W
W
RL
R
R
R
SSA
Figure 10-2. ADC12B16C Register Summary (Sheet 1 of 3)
ETRIGSEL
Reserved
Bit 7
0
S12XS Family Reference Manual, Rev. 1.11
= Unimplemented or Reserved
SRES1
RL
AFFC
6
0
is the low reference voltage for ATD conversion.
ICLKSTP ETRIGLE
SRES0
5
0
NOTE
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
4
0
ETRIGP
WRAP3
3
Analog-to-Digital Converter (ADC12B16CV1)
ETRIGE
WRAP2
2
WRAP1
ASCIE
1
ACMPIE
WRAP0
Bit 0
273

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