S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 28

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Overview S12XS Family
Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return undefined data values.
A CPU access to any unimplemented space causes an illegal address reset.
The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block
sizes are listed in
1.1.6
The detailed register map is listed in the appendix of the reference manual.
1.1.7
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip.
number and Mask Set number.
The Version ID is a word located in a flash information row at 0x40_00E8. The version ID number
indicates a specific version of internal NVM variables used to patch NVM errata. The default is no patch
(0xFFFF).
28
1
2
3
Number of 16K pages addressable via PPAGE register
Number of 4K pages addressing the RAM via PPAGE register
Number of 1K pages addressing the DFLASH via the EPAGE register starting upwards from 0x00
S12XS256
S12XS128
S12XS64
Device
Detailed Register Map
Part ID Assignments
Table 1-2. Derivative Dependent Memory Parameters of Device Internal Resources
1
The coding is as follows:
MC9S12XS256
MC9S12XS128
MC9S12XS64
Bit 15-12: Major family identifier
Bit 11-6: Minor family identifier
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
Table
Device
FLASH_LOW
0x7C_0000
0x7E_0000
0x7F_0000
1-2.
S12XS Family Reference Manual, Rev. 1.11
Table 1-3. Assigned Part ID Numbers
Mask Set Number
256K / 16
PPAGE
128K / 8
64K / 4
SIZE/
0M05M
0M04M
1M04M
0M04M
1M04M
1
0x0F_D000
RAM_LOW
0x0F_E000
0x0F_F000
Part ID
$C0C0
$C1C0
$C1C1
$C1C0
$C1C1
RPAGE
12K / 3
SIZE/
8K / 2
4K / 1
1
Table 1-3
2
0x10_1FFF
0x10_1FFF
0x10_0FFF
DF_HIGH
shows the assigned part ID
Version ID
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
Freescale Semiconductor
EPAGE
SIZE/
8K / 8
8K / 8
4K / 4
3