S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 76

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
1
Port Integration Module (S12XSPIMV1)
2.3.5
2.3.6
76
Address 0x0002 (PRR)
Address 0x0003 (PRR)
Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
DDRA
DDRB
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Port B Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
DDRA7
DDRB7
Port A Data Direction Register (DDRA)
Port B Data Direction Register (DDRB)
0
0
7
7
DDRA6
DDRB6
0
0
6
6
Figure 2-3. Port A Data Direction Register (DDRA)
Figure 2-4. Port B Data Direction Register (DDRB)
Table 2-6. DDRA Register Field Descriptions
Table 2-7. DDRB Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
DDRA5
DDRB5
0
0
5
5
DDRA4
DDRB4
0
0
4
4
Description
Description
DDRA3
DDRB3
3
0
3
0
DDRA2
DDRB2
0
0
2
2
Freescale Semiconductor
DDRA1
DDRB1
Access: User read/write
Access: User read/write
0
0
1
1
DDRA0
DDRB0
0
0
0
0
1
1