S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 505

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.11.1 Low-Voltage Interrupt (LVI)
In FPM, VREG_3V3 monitors the input voltage V
status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when V
interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable
bit LVIE = 1.
17.4.11.2 HTI - High Temperature Interrupt
In FPM VREG monitors the die temperature T
HTDS is set to 1. Vice versa, HTDS is reset to 0 when T
by flag HTIF=1, is triggered by any change of the status bit HTDS if interrupt enable bit HTIE=1.
17.4.11.3 Autonomous Periodical Interrupt (API)
As soon as the configured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated
by flag APIF = 1, is triggered if interrupt enable bit APIE = 1.
Freescale Semiconductor
On entering the Reduced Power Mode, the LVIF is not cleared by the
VREG_3V3.
On entering the Reduced Power Mode the HTIF is not cleared by the VREG.
S12XS Family Reference Manual, Rev. 1.11
DIE
NOTE
NOTE
. Whenever T
DDA
. Whenever V
DIE
get below level T
DIE
exceeds level T
DDA
DDA
drops below level V
Voltage Regulator (S12VREGL3V3V1)
HTID
rises above level V
. An interrupt, indicated
HTIA
the status bit
LVIA,
LVID
the
. An
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