S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 55

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.7
1.7.1
The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The
external trigger allows the user to synchronize ATD conversion to external trigger events.
shows the connection of the external trigger inputs.
Consult the ATD section for information about the analog-to-digital converter module. References to
freeze mode are equivalent to active BDM mode.
1.7.2
Further to the 16 externally available channels, ATD0 features an extra channel[17] that is connected to
the internal temperature sensor at device level. To access this channel ATD0 must use the channel encoding
SC:CD:CC:CB:CA = 1:0:0:0:1 in ATDCTL5. For more temperature sensor information, please refer to
1.8.1 Temperature Sensor
1.8
The device must be configured with the internal voltage regulator enabled. Operation in conjunction with
an external voltage regulator is not supported.
The API trimming register APITR is loaded from the Flash IFR option field at global address 0x40_00F0
bits[5:0] during the reset sequence. Currently factory programming of this IFR range is not supported.
Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does
not support access abort of reserved VREG register space.
1.8.1
The VREG high temperature trimming register bits VREGHTTR[3:0] are loaded from the internal Flash
during the reset sequence. To use the high temperature interrupt within the specified limits (T
T
The device temperature can be monitored on ATD0 channel[17]. The internal bandgap reference voltage
can also be mapped to ATD0 analog input channel[17]. The voltage regulator VSEL bit when set, maps
the bandgap and, when clear, maps the temperature sensor to ATD0 channel[17].
Freescale Semiconductor
HTID
) these bits must be loaded with 0x8. Currently factory programming is not supported.
ATD0 Configuration
VREG Configuration
External Trigger Input Connection
ATD0 Channel[17] Connection
Temperature Sensor Configuration
External Trigger
Configuration.
ETRIG0
ETRIG1
ETRIG2
ETRIG3
Input
Table 1-13. ATD0 External Trigger Sources
S12XS Family Reference Manual, Rev. 1.11
Periodic interrupt timer hardware trigger 0
Periodic interrupt timer hardware trigger 1
Pulse width modulator channel 1
Pulse width modulator channel 3
Connectivity
Device Overview S12XS Family
Table 1-13
HTIA
and
55