S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 453

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the
SPI data register is not transmitted; instead the last received data is transmitted. If the SS line is deasserted
for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the
SPI data register is transmitted.
In master mode, with slave select output enabled the SS line is always deasserted and reasserted between
successive transfers for at least minimum idle time.
15.4.3.3
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin,
the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the
CPHA bit at the beginning of the n
The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first
edge commands the slave to transfer its first data bit to the serial data input pin of the master.
A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the
master and slave.
1.
Freescale Semiconductor
n depends on the selected transfer width, please refer to
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
t
t
t
t
Figure 15-13. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width selected (XFRW = 1)
MOSI pin
MISO pin
L
T
I
L
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
, t
= Minimum idling time between transfers (minimum SS high time)
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
T
, and t
CPHA = 1 Transfer Format
I
are guaranteed for the master mode and required for the slave mode.
MSB
LSB
t
L
1
2
Bit 14
Bit 1
3
4
Bit 13
Bit 2
5
Begin
S12XS Family Reference Manual, Rev. 1.11
6
1
Bit 12
Bit 3
-cycle transfer operation.
7
8
Bit 11
Bit 4
9
10
Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
Bit 5
11
12
Bit 6
13
14
Section 15.3.2.2, “SPI Control Register 2 (SPICR2)
Transfer
Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14
15
16
17
18
19
20
Bit 5
21
22
Bit 4 Bit 3 Bit 2 Bit 1
23
24
25
End
26
27
Serial Peripheral Interface (S12SPIV5)
28
29
30
MSB
LSB
31
32
t
T
Minimum 1/2 SCK
for t
Begin of Idle State
t
I
t
T
L
, t
l
, t
L
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