S9S12XS256J0CAL Freescale Semiconductor, S9S12XS256J0CAL Datasheet - Page 93

• Manufacturer Part Number: S9S12XS256J0CAL
• Description: MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS256J0CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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2.3.28
Freescale Semiconductor
Address 0x0249
Read: Anytime.
Write: Anytime.
DDRS
DDRS
DDRS
Field
Field
PTIS
Reset
7-0
7-4
3-2
1-0
W
R
Port S input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI1 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
DDRS7
Port S Data Direction Register (DDRS)
0
7
DDRS6
0
6
Figure 2-26. Port S Data Direction Register (DDRS)
Table 2-25. DDRS Register Field Descriptions
Table 2-24. PTIS Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.11
DDRS5
0
5
DDRS4
0
4
Description
Description
DDRS3
3
0
DDRS2
0
Port Integration Module (S12XSPIMV1)
2
DDRS1
Access: User read/write
0
1
DDRS0
0
0
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