DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 168

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
Note:
Rev. 2.00 Jun. 28, 2007 Page 142 of 864
REJ09B0341-0200
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
*
Bit Name
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
In burst ROM interface, the CSXTn settings are ignored during CPU read accesses.
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CS and Address Signal Assertion Period Control 1
These bits specify whether or not the Th cycle is to be
inserted (see figure 6.3). When an area for which bit
CSXHn is set to 1 is accessed, one Th cycle, in which the
CSn and address signals are asserted, is inserted before
the normal access cycle.
0: In access to area n, the CSn and address assertion
1: In access to area n, the CSn and address assertion
(n = 7 to 0)
CS and Address Signal Assertion Period Control 2
These bits specify whether or not the Tt cycle is to be
inserted (see figure 6.3). When an area for which bit
CSXTn is set to 1 is accessed, one Tt cycle, in which the
CSn and address signals are retained, is inserted after
the normal access cycle.
0: In access to area n, the CSn and address assertion
1: In access to area n, the CSn and address assertion
(n = 7 to 0)
period (Th) is not extended
period (Th) is extended
period (Tt) is not extended
period (Tt) is extended