DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 20

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 Programmable Pulse Generator (PPG)............................................ 491
11.1 Features.............................................................................................................................. 491
11.2 Input/Output Pins............................................................................................................... 492
11.3 Register Descriptions......................................................................................................... 493
11.4 Operation ........................................................................................................................... 502
11.5 Usage Notes ....................................................................................................................... 510
Section 12 8-Bit Timers (TMR) ........................................................................ 511
12.1 Features.............................................................................................................................. 511
12.2 Input/Output Pins............................................................................................................... 514
12.3 Register Descriptions......................................................................................................... 514
12.4 Operation ........................................................................................................................... 525
12.5 Operation Timing............................................................................................................... 527
Rev. 2.00 Jun. 28, 2007 Page xviii of xxiv
11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 493
11.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 495
11.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 496
11.3.4 PPG Output Control Register (PCR) .................................................................... 499
11.3.5 PPG Output Mode Register (PMR) ...................................................................... 500
11.4.1 Output Timing ...................................................................................................... 502
11.4.2 Sample Setup Procedure for Normal Pulse Output............................................... 503
11.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)................ 504
11.4.4 Non-Overlapping Pulse Output............................................................................. 505
11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 507
11.4.6 Example of Non-Overlapping Pulse Output
11.4.7 Inverted Pulse Output ........................................................................................... 509
11.4.8 Pulse Output Triggered by Input Capture ............................................................. 510
11.5.1 Module Stop State Setting .................................................................................... 510
11.5.2 Operation of Pulse Output Pins............................................................................. 510
12.3.1 Timer Counter (TCNT)......................................................................................... 516
12.3.2 Time Constant Register A (TCORA) ................................................................... 516
12.3.3 Time Constant Register B (TCORB).................................................................... 517
12.3.4 Timer Control Register (TCR).............................................................................. 517
12.3.5 Timer Counter Control Register (TCCR) ............................................................. 519
12.3.6 Timer Control/Status Register (TCSR)................................................................. 521
12.4.1 Pulse Output ......................................................................................................... 525
12.4.2 Reset Input............................................................................................................ 526
12.5.1 TCNT Count Timing ............................................................................................ 527
12.5.2 Timing of CMFA and CMFB Setting at Compare Match .................................... 528
(Example of 4-Phase Complementary Non-Overlapping Pulse Output) .............. 507