DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 21

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6 Operation with Cascaded Connection................................................................................ 531
12.7 Interrupt Sources................................................................................................................ 532
12.8 Usage Notes ....................................................................................................................... 533
Section 13 Watchdog Timer (WDT)..................................................................539
13.1 Features.............................................................................................................................. 539
13.2 Input/Output Pin................................................................................................................. 540
13.3 Register Descriptions ......................................................................................................... 540
13.4 Operation ........................................................................................................................... 544
13.5 Interrupt Source ................................................................................................................. 546
13.6 Usage Notes ....................................................................................................................... 546
12.5.3 Timing of Timer Output at Compare Match ......................................................... 528
12.5.4 Timing of Counter Clear by Compare Match ....................................................... 529
12.5.5 Timing of TCNT External Reset........................................................................... 529
12.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 530
12.6.1 16-Bit Counter Mode ............................................................................................ 531
12.6.2 Compare Match Count Mode................................................................................ 531
12.7.1 Interrupt Sources and DTC Activation ................................................................. 532
12.7.2 A/D Converter Activation..................................................................................... 532
12.8.1 Notes on Setting Cycle.......................................................................................... 533
12.8.2 Conflict between TCNT Write and Clear ............................................................. 533
12.8.3 Conflict between TCNT Write and Increment...................................................... 534
12.8.4 Conflict between TCOR Write and Compare Match ............................................ 534
12.8.5 Conflict between Compare Matches A and B....................................................... 535
12.8.6 Switching of Internal Clocks and TCNT Operation.............................................. 535
12.8.7 Mode Setting with Cascaded Connection ............................................................. 537
12.8.8 Module Stop Function Setting .............................................................................. 537
12.8.9 Interrupts in Module Stop State ............................................................................ 537
13.3.1 Timer Counter (TCNT)......................................................................................... 540
13.3.2 Timer Control/Status Register (TCSR)................................................................. 541
13.3.3 Reset Control/Status Register (RSTCSR)............................................................. 542
13.4.1 Watchdog Timer Mode ......................................................................................... 544
13.4.2 Interval Timer Mode............................................................................................. 545
13.6.1 Notes on Register Access...................................................................................... 546
13.6.2 Conflict between Timer Counter (TCNT) Write and Increment........................... 547
13.6.3 Changing Values of Bits CKS2 to CKS0.............................................................. 548
13.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 548
13.6.5 Internal Reset in Watchdog Timer Mode.............................................................. 548
13.6.6 System Reset by WDTOVF Signal....................................................................... 548
13.6.7 Transition to Watchdog Timer Mode or Software Standby Mode........................ 549
Rev. 2.00 Jun. 28, 2007 Page xix of xxiv