DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 632

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI)
Rev. 2.00 Jun. 28, 2007 Page 606 of 864
REJ09B0341-0200
Note: When switching from transmit or receive operation to simultaneous transmit and receive
Figure 14.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
No
No
No
Clear TE and RE bits in SCR to 0
Read receive data in RDR, and
Write transmit data to TDR and
Start transmission/reception
clear TDRE flag in SSR to 0
clear RDRF flag in SSR to 0
Read ORER flag in SSR
Read TDRE flag in SSR
Read RDRF flag in SSR
All data received?
Initialization
ORER = 1
RDRF = 1
TDRE = 1
<End>
Yes
Yes
Yes
No
Error processing
Yes
[1]
[2]
[4]
[5]
[3]
[1] SCI initialization:
[2] SCI state check and transmit data write:
[3] Receive error processing:
[4] SCI state check and receive data read:
[5] Serial transmission/reception continuation
The TxD pin is designated as the transmit data
output pin, and the RxD pin is designated as the
receive data input pin, enabling simultaneous
transmit and receive operations.
Read SSR and check that the TDRE flag is set to 1,
then write transmit data to TDR and clear the TDRE
flag to 0. Transition of the TDRE flag from 0 to 1
can also be identified by a TXI interrupt.
If a receive error occurs, read the ORER flag in
SSR, and after performing the appropriate error
processing, clear the ORER flag to 0. Reception
cannot be resumed if the ORER flag is set to 1.
Read SSR and check that the RDRF flag is set to 1,
then read the receive data in RDR and clear the
RDRF flag to 0. Transition of the RDRF flag from 0
to 1 can also be identified by an RXI interrupt.
procedure:
To continue serial transmission/ reception, before
the MSB (bit 7) of the current frame is received,
finish reading the RDRF flag, reading RDR, and
clearing the RDRF flag to 0. Also, before the MSB
(bit 7) of the current frame is transmitted, read 1
from the TDRE flag to confirm that writing is
possible. Then write data to TDR and clear the
TDRE flag to 0.
However, the TDRE flag is checked and cleared
automatically when the DMAC or DTC is initiated
by a transmit data empty interrupt (TXI) request and
writes data to TDR. Similarly, the RDRF flag is
cleared automatically when the DMAC or DTC is
initiated by a receive data full interrupt (RXI) and
reads data from RDR.