DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 885

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Numerics
0-output/1-output .................................... 448
16-bit access space.................................. 173
16-bit counter mode................................ 531
16-bit timer pulse unit (TPU) ................. 405
8-bit access space.................................... 172
8-bit timers (TMR) ................................. 511
A
A/D conversion accuracy........................ 637
A/D converter ......................................... 625
Absolute accuracy................................... 637
Address error ............................................ 82
Address map ............................................. 71
Address modes........................................ 259
Address/data multiplexed
I/O interface.................................... 166, 201
All-module-clock-stop mode .......... 756, 767
Area 0 ..................................................... 167
Area 1 ..................................................... 167
Area 2 ..................................................... 168
Area 3 ..................................................... 168
Area 4 ..................................................... 169
Area 5 ..................................................... 170
Area 6 ..................................................... 170
Area 7 ..................................................... 171
Area division........................................... 161
Asynchronous mode ............................... 583
AT-cut parallel-resonance type............... 749
Available output signals and settings
in each port ............................................. 386
Average transfer rate generator............... 552
B
Bφ clock output control .......................... 777
Index
Basic bus interface .......................... 165, 175
Big endian ............................................... 164
Bit rate..................................................... 574
Block structure ........................................ 656
Block transfer mode ........................ 264, 330
Boot mode....................................... 653, 681
Burst mode.............................................. 270
Burst ROM interface....................... 165, 196
Bus arbitration......................................... 227
Bus configuration.................................... 153
Bus controller (BSC)............................... 129
Bus cycle division ................................... 324
Bus modes............................................... 269
Bus width ................................................ 164
Bus-released state...................................... 61
Byte control SRAM interface ......... 165, 188
C
Cascaded connection............................... 531
Cascaded operation ................................. 457
Chain transfer.......................................... 331
Chip select signals................................... 162
Clock pulse generator ............................. 745
Clock synchronization cycle (Tsy).......... 155
Clocked synchronous mode .................... 600
Communications protocol ....................... 715
Compare match A ................................... 528
Compare match B ................................... 529
Compare match count mode ................... 531
Compare match signal............................. 528
CPU priority control function
over DTC and DMAC............................. 122
Crystal resonator ..................................... 749
Cycle stealing mode................................ 269
Rev. 2.00 Jun. 28, 2007 Page 859 of 864
REJ09B0341-0200