DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 645

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.8.2
Table 14.13 shows the interrupt sources in smart card interface mode. A transmit end (TEI)
interrupt request cannot be used in this mode.
Table 14.13 SCI Interrupt Sources
Data transmission/reception using the DMAC or DTC is also possible in smart card interface
mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are
simultaneously set to 1, thus generating a TXI interrupt. This activates the DMAC or DTC by a
TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of
DMAC or DTC activation beforehand. The TDRE and TEND flags are automatically cleared to 0
at data transfer by the DMAC or DTC. If an error occurs, the SCI automatically re-transmits the
same data. During re-transmission, the TEND flag remains as 0, thus not activating the DMAC or
DTC. Therefore, the SCI and DMAC or DTC automatically transmit the specified number of
bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR,
which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by
previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at
error occurrence.
When transmitting/receiving data using the DMAC or DTC, be sure to set and enable the DMAC
or DTC prior to making SCI settings. For DMAC settings, see section 7, DMA Controller
(DMAC), and for DTC settings, see section 8, Data Transfer Controller (DTC).
In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This
activates the DMAC or DTC by an RXI request thus allowing transfer of receive data if the RXI
request is specified as a source of DMAC or DTC activation beforehand. The RDRF flag is
automatically cleared to 0 at data transfer by the DMAC or DTC. If an error occurs, the RDRF
flag is not set but the error flag is set. Therefore, the DMAC or DTC is not activated and an ERI
interrupt request is issued to the CPU instead; the error flag must be cleared.
Name
ERI
RXI
TXI
Interrupts in Smart Card Interface Mode
Receive data full
Transmit data empty
Interrupt Source
Receive error or error
signal detection
Interrupt Flag
ORER, PER, or
ERS
RDRF
TDRE
Section 14 Serial Communication Interface (SCI)
DTC
Activation
Not possible
Possible
Possible
Rev. 2.00 Jun. 28, 2007 Page 619 of 864
DMAC
Activation
Not possible
Possible
Possible
REJ09B0341-0200
Priority
High
Low