DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 280

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
Rev. 2.00 Jun. 28, 2007 Page 254 of 864
REJ09B0341-0200
Bit
19, 18
17
16
15
14, 13
Bit Name

DAT1
DAT0
SARIE

Initial
Value
All 0
0
0
0
All 0
R/W
R
R/W
R/W
R/W
R
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Destination Address Update Mode 1 and 0
Select the update method of the destination address
(DDAR). When DDAR is not specified as the transfer
destination in single address mode, this bit is ignored.
00: Destination address is fixed
01: Destination address is updated by adding the offset
10: Destination address is updated by adding 1, 2, or 4
11: Destination address is updated by subtracting 1, 2,
Interrupt Enable for Source Address Extended Area
Overflow
Enables/disables an interrupt request for an extended
area overflow on the source address.
When an extended repeat area overflow on the source
address occurs while this bit is set to 1, the DTE bit in
DMDR is cleared to 0. At this time, the ESIF bit in
DMDR is set to 1 to indicate an interrupt by an extended
repeat area overflow on the source address is
requested.
When block transfer mode is used with the extended
repeat area function, an interrupt is requested after
completion of a 1-block size transfer. When setting the
DTE bit in DMDR of the channel for which a transfer has
been stopped to 1, the transfer is resumed from the
state when the transfer is stopped.
When the extended repeat area is not specified, this bit
is ignored.
0: Disables an interrupt request for an extended area
1: Enables an interrupt request for an extended area
Reserved
These bits are always read as 0 and cannot be
modified.
overflow on the source address
overflow on the source address
according to the data access size
or 4 according to the data access size