DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 366

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
8.7.3
By executing a second data transfer and performing re-setting of the first data transfer only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 8.16 shows the chain transfer when the
counter value is 0.
1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source
2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first
3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for re-
4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter
5. Next, execute the first data transfer the 65536 times specified for the first data transfer by
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
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address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0.
data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at
addresses H'200000 to H'21FFFF, prepare H'21 and H'20.
setting the transfer destination address for the first data transfer. Use the upper eight bits of
DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0.
If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits
of the transfer source address for the first data transfer to H'21. The lower 16 bits of the
transfer destination address of the first data transfer and the transfer counter are H'0000.
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper eight bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
no interrupt request is sent to the CPU.
Chain Transfer when Counter = 0