DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 294

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
Table 7.5
(3)
A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA
transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. When a DMA
transfer between on-chip peripheral modules is performed, select an activation source from the
auto request and on-chip module interrupt (the external request cannot be used).
A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling
edge or low level. Whether the falling edge or low level detection is used is selected by the
DREQS bit in DMDR. To perform a block transfer, select the low level detection (DREQS = 0).
When an external request is selected as an activation source, clear the DDR bit to 0 and set the
ICR bit to 1 for the corresponding pin. For details, see section 9, I/O Ports.
Rev. 2.00 Jun. 28, 2007 Page 268 of 864
REJ09B0341-0200
On-Chip Module Interrupt Source
ADI (conversion end interrupt for A/D converter)
TGI0A (TGI0A input capture/compare match)
TGI1A (TGI1A input capture/compare match)
TGI2A (TGI2A input capture/compare match)
TGI3A (TGI3A input capture/compare match)
TGI4A (TGI4A input capture/compare match)
TGI5A (TGI5A input capture/compare match)
RXI0 (receive data full interrupt for SCI channel 0)
TXI0 (transmit data empty interrupt for SCI channel 0)
RXI1 (receive data full interrupt for SCI channel 1)
TXI1 (transmit data empty interrupt for SCI channel 1)
RXI2 (receive data full interrupt for SCI channel 2)
TXI2 (transmit data empty interrupt for SCI channel 2)
RXI4 (receive data full interrupt for SCI channel 4)
TXI4 (transmit data empty interrupt for SCI channel 4)
Activation by External Request
List of On-chip module interrupts to DMAC
On-Chip
Module
A/D
TPU_0
TPU_1
TPU_2
TPU_3
TPU_4
TPU_5
SCI_0
SCI_0
SCI_1
SCI_1
SCI_2
SCI_2
SCI_4
SCI_4
DMRSR
(Vector
Number)
86
88
93
97
101
106
110
145
146
149
150
153
154
161
162