DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 309

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 7.22 shows a transfer example when multiple transfer requests from channels 0 to 2.
7.5.9
Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is
transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When
the bus mastership is passed from the DMAC to the CPU, data is read from the source address and
it is written to the destination address. The bus is not released between the read and write cycles
by other bus requests. DMAC bus cycles follows the bus controller settings.
Bφ
Address bus
DMAC
operation
Channel 0
Channel 1
Channel 2
Bφ
Address bus
RD
LHWR
LLWR
DMA Basic Bus Cycle
High
CPU cycle
Wait
Request
retained
Request
retained
Figure 7.23 Example of Bus Timing of DMA Transfer
Figure 7.22 Example of Timing for Channel Priority
Request cleared
Channel 0
Selected
Not
selected
Source address
T
1
Channel 0 transfer
Request
retained
T
2
Request cleared
Channel 0
T
1
DMAC cycle (one word transfer)
Channel 1
T
Selected
Bus
released
2
Destination address
Channel 1 transfer
T
3
Request cleared
Channel 1
Rev. 2.00 Jun. 28, 2007 Page 283 of 864
T
1
Channel 2
Section 7 DMA Controller (DMAC)
T
Bus
released
2
T
3
Channel 2 transfer
REJ09B0341-0200
Channel 2
CPU cycle
Wait