DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 319

IC H8SX/1657 MCU FLASH 120TQFP

DF61657CN35FTV

Manufacturer Part Number
DF61657CN35FTV
Description
IC H8SX/1657 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of DF61657CN35FTV

Core Processor
H8SX
Core Size
32-Bit
Speed
35MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
82
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF61657CN35FTV
Manufacturer:
RENESAS
Quantity:
101
Part Number:
DF61657CN35FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.5.11
(1)
In single address mode, one byte, one word, or one longword of data is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU or DTC are executed in the bus released cycles.
In figure 7.34, the TEND signal output is enabled and data is transferred in bytes from the external
8-bit 2-state access space to the external device in single address mode (read).
Single Address Mode (Read and Cycle Stealing)
Bus Cycles in Single Address Mode
Figure 7.34 Example of Transfer in Single Address Mode (Byte Read)
Address bus
RD
DACK
TEND
released
Bus
DMA read
cycle
released
Bus
DMA read
cycle
released
Bus
DMA read
cycle
Rev. 2.00 Jun. 28, 2007 Page 293 of 864
released
Bus
Section 7 DMA Controller (DMAC)
Last transfer
DMA read
cycle
cycle
released
Bus
REJ09B0341-0200

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