DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 533

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.4.5
Figure 11.8 shows a sample procedure for setting up non-overlapping pulse output.
11.4.6
Figure 11.9 shows an example in which pulse output is used for 4-phase complementary non-
overlapping pulse output.
PPG setup
TPU setup
TPU setup
Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
Sample Setup Procedure for Non-Overlapping Pulse Output
Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary
Non-Overlapping Pulse Output)
Set non-overlapping groups
Set counting operation
Select interrupt request
Select TGR functions
Set initial output data
Enable pulse output
Select output trigger
Compare match A?
Non-overlapping
Set TGR values
Set next pulse
Set next pulse
Start counter
pulse output
output data
output data
Yes
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
Section 11 Programmable Pulse Generator (PPG)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Set the CST bit in TSTR to 1 to start the
[11] At each TGIA interrupt, set the next
Set TIOR to make TGRA and TGRB
output compare registers (with output
disabled).
Set the pulse output trigger cycle in
TGRB and the non-overlapping margin
in TGRA.
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the
counter clear source with bits CCLR1
and CCLR0.
Enable the TGIA interrupt in TIER. The
DTC or DMAC can also be set up to
transfer data to NDR.
Set the initial output values in PODR.
Set the bits in NDER for the pins to be
used for pulse output to 1.
Select the TPU compare match event to
be used as the pulse output trigger in
PCR.
In PMR, select the groups that will
operate in non-overlapping mode.
Set the next pulse output values in NDR.
TCNT counter.
output values in NDR.
Rev. 2.00 Jun. 28, 2007 Page 507 of 864
REJ09B0341-0200