DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 298

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)
7.5.6
The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or
offset addition. When the offset addition is selected, the offset specified by the offset register
(DOFR) is added to the address every time the DMAC transfers the data access size of data. This
function realizes a data transfer where addresses are allocated to separated areas.
Figure 7.17 shows the address update method.
Rev. 2.00 Jun. 28, 2007 Page 272 of 864
REJ09B0341-0200
Figure 7.16 Example of Extended Repeat Area Function in Block Transfer Mode
When the are represented by the lower three bits (eight bytes) of DSAR are specified as the extended
repeat area (SARA4 to SARA0 = 3) and the block size in block transfer mode is specified to 5 (bits 23
to 16 in DTCR = 5).
Address Update Function using Offset
(a) Address fixed
Address not
updated
External memory Area specified
H'23FFFE
H'23FFFF
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
H'240008
H'240009
±0
Figure 7.17 Address Update Method
by DSAR
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
(b) Increment or decrement
Data access size
added to or subtracted
from address (addresses
are continuous)
by 1, 2, or 4
1st block
transfer
H'240000
H'240001
H'240002
H'240003
H'240004
±1, 2, or 4
2nd block
transfer
H'240000
H'240001
H'240005
H'240006
H'240007
Offset is added to address
(addresses are not
continuous)
(c) Offset addition
Block transfer
continued
Interrupt
request
generated
+ offset