DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 443

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3.2
TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each
channel. TMDR register settings should be made only while TCNT operation is stopped.
Bit
7, 6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name

BFB
BFA
MD3
MD2
MD1
MD0
Timer Mode Register (TMDR)

R
7
1
Initial
Value
All 1
0
0
0
0
0
0

R
6
1
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
BFB
R/W
5
0
Description
Reserved
These are read-only bits and cannot be modified.
Buffer Operation B
Specifies whether TGRB is to normally operate, or TGRB
and TGRD are to be used together for buffer operation.
When TGRD is used as a buffer register, TGRD input
capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation A
Specifies whether TGRA is to normally operate, or TGRA
and TGRC are to be used together for buffer operation.
When TGRC is used as a buffer register, TGRC input
capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
Modes 3 to 0
Set the timer operating mode.
MD3 is a reserved bit. The write value should always be
0. For details, see table 10.12 for details.
R/W
BFA
4
0
MD3
R/W
3
0
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Jun. 28, 2007 Page 417 of 864
MD2
R/W
2
0
MD1
R/W
1
0
REJ09B0341-0200
MD0
R/W
0
0