DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 805

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified according to functional modules.
• The number of Access Cycles indicates the number of states based on the specified reference
• Among the internal I/O register area, addresses not listed in the list of registers are undefined
2. Register bits
• Bit configurations of the registers are listed in the same order as the register addresses.
• Reserved bits are indicated by  in the bit name column.
• Space in the bit name field indicates that the entire register is allocated to either the counter or
• For the registers of 16 or 32 bits, the MSB is listed first.
3. Register states in each operating mode
• Register states are listed in the same order as the register addresses.
• For the initialized state of each bit, refer to the register description in the corresponding
• The register states shown here are for the basic operating modes. If there is a specific reset for
clock. For details, refer to section 6.5.4, External Bus Interface.
or reserved addresses. Undefined and reserved addresses cannot be accessed. Do not access
these addresses; otherwise, the operation when accessing these bits and subsequent operations
cannot be guaranteed.
data.
Byte configuration description order is subject to big endian.
section.
an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Section 21 List of Registers
Rev. 2.00 Jun. 28, 2007 Page 779 of 864
Section 21 List of Registers
REJ09B0341-0200