DF61657CN35FTV Renesas Electronics America, DF61657CN35FTV Datasheet - Page 234

• Manufacturer Part Number: DF61657CN35FTV
• Description: IC H8SX/1657 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61657CN35FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 35MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: 3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.9.9
In the address/data multiplexed interface, the extension cycles can be inserted before and after the
bus cycle. For details, see section 6.6.6, Extension of Chip Select (CS) Assertion Period.
Figure 6.34 shows an example of the chip select (CS) assertion period extension timing.
When consecutively reading from the same area connected to a peripheral LSI whose data hold
time is long, data outputs from the peripheral LSI and this LSI may conflict. Inserting the chip
select assertion period extension cycle after the access cycle can avoid the data conflict.
Figure 6.35 shows an example of the operation. In the figure, both bus cycles A and B are read
access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown
in (a), and an example of avoiding the data conflict by the CS assertion period extension cycle in
(b).
Rev. 2.00 Jun. 28, 2007 Page 208 of 864
REJ09B0341-0200
Figure 6.34 Chip Select (CS) Assertion Period Extension Timing in Data Cycle
Read
Write
Extension of Chip Select (CS) Assertion Period
Bφ
Address bus
CSn
AH
RD
D15 to D0
LHWR
LLWR
D15 to D0
BS
RD/WR
DACK
Note: n = 3 to 7
T
ma1
Address cycle
Address
Address
T
ma2
T
h
Bus cycle
T
1
Data cycle
Write data
T
Read data
2
T
t