HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 109

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STC.L
STS
STS
STS
STS.L
STS.L
STS.L
TRAPA
Notes: The table shows the minimum number of clocks required for execution. In practice, the
Instruction
number of execution cycles will be increased in the following conditions.
For addressing modes with displacement (disp) as shown below, the assembler description
in this manual indicates the value before it is scaled (x 1, x2, or x4) according to the
operand size to clarify the LSI operation. For details on assembler description, refer to the
description rules in each assembler.
1. Number of states before the chip enters the sleep state.
2. For details, refer to section 5, Exception Handling.
SSR,@–Rn
SPC,@–Rn
R0_BANK,@–Rn
R1_BANK,@–Rn
R2_BANK,@–Rn
R3_BANK,@–Rn
R4_BANK,@–Rn
R5_BANK,@–Rn
R6_BANK,@–Rn
R7_BANK,@–Rn
MACH,Rn
MACL,Rn
PR,Rn
MACH,@–Rn
MACL,@–Rn
PR,@–Rn
#imm
a.
b.
If the destination register of a load instruction (memory
used by the following instruction.
If there is a conflict between an instruction fetch and a data access
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, Rn) ; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp ; PC relative
Instruction
Code
0100nnnn00110011
0100nnnn01000011
0100nnnn10000011
0100nnnn10010011
0100nnnn10100011
0100nnnn10110011
0100nnnn11000011
0100nnnn11010011
0100nnnn11100011
0100nnnn11110011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0100nnnn00000010
0100nnnn00010010
0100nnnn00100010
11000011iiiiiiii
Operation
Rn–4 Rn, SSR (Rn)
Rn–4 Rn, SPC (Rn)
Rn–4 Rn, R0_BANK (Rn)
Rn–4 Rn, R1_BANK (Rn)
Rn–4 Rn, R2_BANK (Rn)
Rn–4 Rn, R3_BANK (Rn)
Rn–4 Rn, R4_BANK (Rn)
Rn–4 Rn, R5_BANK (Rn)
Rn–4 Rn, R6_BANK (Rn)
Rn–4 Rn, R7_BANK (Rn)
MACH Rn
MACL Rn
PR Rn
Rn–4 Rn, MACH (Rn)
Rn–4 Rn, MACL (Rn)
Rn–4 Rn, PR (Rn)
Unconditional trap exception
occurs *
2
Rev. 2.00, 09/03, page 61 of 690
Privileged
Mode
–
–
–
–
–
–
–
register) is also
Cycles T Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–