HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 289

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.2
The external pins for the DMAC are described below.
Table 8.1 lists the configuration of the pins that are connected to external bus. The DMAC has
pins for 2 channels (channels 0 and 1) for external bus use. Channel 0 has the DMA transfer end
signal.
Table 8.1
Channel Name
0
1
8.3
The DMAC has the following registers. See section 24, List of Registers, for the addresses of
these registers and the states of them in each processing state. The SAR for channel 0 is expressed
such as SAR_0.
1. Channel 0
2. Channel 1
DMA source address register_0 (SAR_0)
DMA destination address register_0 (DAR_0)
DMA transfer count register_0 (DMATCR_0)
DMA channel control register_0 (CHCR_0)
DMA source address register_1 (SAR_1)
DMA destination address register_1 (DAR_1)
DMA transfer count register_1 (DMATCR_1)
DMA channel control register _1 (CHCR_1)
Register Descriptions
Input/Output Pins
DMA transfer request
DMA transfer request
acknowledge
DMA transfer end
DMA transfer request
DMA transfer request
acknowledge
Pin Configuration
Symbol
DREQ0
DACK0
TEND0
DREQ1
DACK1
I/O
I
O
O
O
I
Function
DMA transfer request input from
external device to channel 0
DMA transfer request acknowledge
output from channel 0 to external device
Transfer end output in channel 0
DMA transfer request input from
external device to channel 1
DMA transfer request acknowledge
output from channel 1 to external device
Rev. 2.00, 09/03, page 241 of 690